The present invention generally relates to methods of forming semiconductor devices. More particularly, the present invention relates to methods of forming semiconductor devices having capacitors including electrodes comprising metal.
A capacitor in an integrated circuit (semiconductor) device typically includes a bottom electrode, an upper electrode and a dielectric layer interposed between the bottom electrode and the upper electrode. Such a capacitor may be used, for example, in a data-storing memory cell or as part of a logic circuit. As semiconductor devices become highly integrated, the size of capacitors included in the device are generally reduced, which may decrease the capacitance of the capacitors.
In some integrated circuits, the bottom electrode and the upper electrode of a capacitor may be conventionally formed of polysilicon doped by impurities and the dielectric layer may be conventionally formed of silicon oxide and/or an oxide-nitride-oxide (ONO) layer. A native oxide layer may be formed on the polysilicon doped by impurities. The capacitance of the capacitor may be decreased due to the native oxide layer because the native oxide layer may increase an overall thickness of the dielectric layer. Accordingly, various investigations have been undertaken directed to increasing capacitance while decreasing physical planar area of a capacitor.
One area of investigation is metal-insulator-metal (MIM) capacitors wherein the bottom electrode and the upper electrode are formed as metal layers. A MIM capacitor may store more charge than a capacitor using electrodes of a polysilicon doped by impurities as the use of metal may prevent the formation of the native oxide layer. Furthermore, the MIM capacitor may employ a high-k dielectric layer having a higher dielectric constant (k) than the ONO layer described above for the doped polysilicon electrode capacitor. Thus, capacitance of the MIM capacitor may be increased. The MIM capacitor may be used, for example, in a data-storing memory cell of a dynamic random access memory (DRAM) device and/or a ferroelectric memory device.
However, a bottom electrode of the MIM capacitor may be disposed on a conductive plug formed of a polysilicon doped by impurities. As such, due to a difference of a work function between the bottom electrode of metal and the conductive plug of polysilicon, a contact resistance therebetween may be increased. As one approach to avoiding this problem, the conductive plug may be formed of a metal layer. However, to form the conductive plug of a metal layer, different equipment may be required, which may increase the cost of forming such a semiconductor device.